Job Description

description of job

Formal Verification Engineer

We are looking for an experienced engineer who has good experience in Formality. This is with our client who are a fast growing and highly innovative company that offers intelligent security solutions. They are market leaders in network and surveillance cameras and are using this as the core around solutions to create a safer and smarter world.

Total Experience:5+ Years  

  • BE/BTech/ME/MTech with E&C.
  • Proven expertise in logic equivalent checking gates-to-gates, gates to power-aware gates using Formality.  
  •  Knowledge of Verilog/VHDL.
  •  Expert in logic equivalence checks using LEC RTL to Netlist, Netlist to Netlist.
  •  Expert in low power checks Good understanding of UPF.
  •  Expert in Synthesis with Synopsys tools Design Compiler and Design Compiler Topographical
  •  Perl and TCL/TK required to achieve highly automated, reproducible and fast results.

Interested candidates can send their resume to vaishak.asok@swediumglobal.com

Job Overview

  • Location : Lund, Sweden
  • Vacancy : 1
  • Key Skills : Synopsys Formality, Synthesis, Verilog, VHDL